ติดตาม
Masato Edahiro
Masato Edahiro
Nagoya University
ยืนยันอีเมลแล้วที่ ertl.jp
ชื่อ
อ้างโดย
อ้างโดย
ปี
A clustering-based optimization algorithm in zero-skew routings
M Edahiro
Proceedings of the 30th international Design Automation Conference, 612-616, 1993
2801993
Practical use of bucketing techniques in computational geometry
T Asano, M Edahiro, I Hiroshi, IRI Masao, K Murota
Machine Intelligence and Pattern Recognition 2, 153-195, 1985
1411985
Information communication device and program execution environment control method
H Inoue, J Sakai, T Abe, M Edahiro
US Patent 8,640,194, 2014
1282014
Data transfer matters for GPU computing
Y Fujii, T Azumi, N Nishio, S Kato, M Edahiro
2013 International Conference on Parallel and Distributed Systems, 275-282, 2013
1132013
Information processing device comprising a plurality of domains having a plurality of processors, recovery device, program and recovery method
H Inoue, J Sakai, T Abe, M Uekubo, N Suzuki, M Edahiro
US Patent 8,365,021, 2013
872013
Power and performance characterization and modeling of GPU-accelerated systems
Y Abe, H Sasaki, S Kato, K Inoue, M Edahiro, M Peres
2014 IEEE 28th international parallel and distributed processing symposium …, 2014
842014
A 600MIPS 120mW 70/spl mu/A leakage triple-CPU mobile application processor chip
S Torii, S Suzuki, H Tomonaga, T Tokue, J Sakai, N Suzuki, K Murakami, ...
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State …, 2005
772005
Delay minimization for zero-skew routing
M Edahiro
IEEE International Conference on Computer Aided Design, 563-563, 1993
731993
An efficient zero-skew routing algorithm
M Edahiro
Proceedings of the 31st annual Design Automation Conference, 375-380, 1994
721994
Multiple processor system, system structuring method in multiple processor system and program thereof
H Inoue, J Sakai, T Abe, M Edahiro
US Patent App. 12/447,513, 2010
662010
Minimum skew and minimum path length routing in VLSI layout design
M Edahiro
NEC Research and Development, 569-575, 1991
641991
Laser beam machining apparatus
Y Onoma, M Edahiro
US Patent 6,239,406, 2001
542001
Interconnect design strategy: structures, repeaters and materials with strategic system performance analysis (S/sup 2/PAL) model
S Takahashi, M Edahiro, Y Hayashi
IEEE Transactions on Electron Devices 48 (2), 239-251, 2001
542001
Traffic light recognition using high-definition map features
M Hirabayashi, A Sujiwo, A Monrroy, S Kato, M Edahiro
Robotics and Autonomous Systems 111, 62-72, 2019
532019
A 1 GIPS 1 W single-chip tightly-coupled four-way multiprocessor with architecture support for multiple control flow execution
N Nishi, T Inoue, M Nomura, S Matsushita, S Torii, A Shibayama, J Sakai, ...
2000 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2000
532000
Pure pursuit revisited: field testing of autonomous vehicles in urban areas
H Ohta, N Akai, E Takeuchi, S Kato, M Edahiro
2016 IEEE 4th International Conference on Cyber-Physical Systems, Networks …, 2016
512016
A single-chip multiprocessor for smart terminals
M Edahiro, S Matsushita, M Yamashina, N Nishi
IEEE Micro 20 (4), 12-20, 2000
482000
Minimum path-length equidistant routing
M Edahiro
Proc. Asia-Pacific Conference on Circuits and Systems (APCCAS), 1992, 1992
411992
Monocular vision-based localization using ORB-SLAM with LIDAR-aided mapping in real-world robot challenge
A Sujiwo, T Ando, E Takeuchi, Y Ninomiya, M Edahiro
Journal of robotics and mechatronics 28 (4), 479-490, 2016
372016
Parallelizing fundamental algorithms such as sorting on multi-core processors for EDA acceleration
M Edahiro
2009 Asia and South Pacific Design Automation Conference, 230-233, 2009
372009
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บทความ 1–20